This invention relates generally to analog-to-digital conversion and more particularly to sigma-delta analog-to-digital conversion.
Analog-to-digital (A/D) conversion, including sigma-delta A/D converters, are known in the art. In general, A/D conversion serves to translate a given analog electrical signal (over a given range of potential signal values) into a series of corresponding digital counterparts. Such conversions are typically not 100% accurate and such inaccuracy gives rise to various artifacts including quantization noise and harmonic distortion. One source of such error lies with variability amongst the elements (current sources, resisters, and so forth) that comprise the digital-to-analog (D/A) converter that is embedded within the negative feedback loop of a sigma-delta A/D. Various prior art techniques have been proposed to attempt to minimize such noise under at least some operating conditions.
Dynamic element matching (DEM) is also known in the art. DEM has been previously used with Nyquist-based A/D conversion to select (either randomly or pursuant to a so-called calibration scheme) specific elements in the embedded D/A to thereby attempt to offset creation of some of the above artifacts. Typically, such approaches have tended to reduce harmonic distortion while raising the overall noise floor. For some applications this has been acceptable but satisfactory application has been limited.
To produce an A/D converter with improved resolution, one must use more bits, a faster clock, and/or more complicated noise shaping strategies. Notwithstanding some limited success, prior use of DEM (including variations known as individual level averaging and data weighted averaging) has not worked well to facilitate improved resolution in an A/D converter. One significant obstacle has been the propagation delay inherent to such an approach as versus the need to provide a relatively current negative feedback signal in the sigma-delta A/D converter. The more stale the feedback signal, the more likely the ultimate conversion will suffer errors and hence unwanted artifacts. Typically an A/D converter will output a next digital representation with each succeeding clock signal. Prior solutions have either required multiple clock cycles to support a large number of bits and/or unit elements (in the feedback loop D/A converter), thereby assuring that the feedback loop information will be stale as compared to the input information, or have limited the number of bits (typically 3 or 4) and/or unit elements of the feedback loop D/A converter (typically 8 to 16) to ensure that the feedback signal can be processed and presented in a timely fashion. These upward limits have retarded an ability to design an A/D converter supporting more bits and unit elements and hence, higher resolution.
A continuing need exists for a way to facilitate the design and fabrication of a sigma-delta analog-to-digital converter that can utilize more bits and unit elements and thereby achieve better resolution (over a given signal bandwidth) and/or a greater signal bandwidth with comparable resolution.